In the field of semiconductor fabrication, the use of dielectric materials having a low dielectric constant (k<2.5), known as low-K materials, is well known. Low-K dielectrics are used primarily in backend processing. Backend processing refers generally to processing subsequent to the formation of transistors in the wafer substrate to interconnect the transistors, typically with multiple levels of metal interconnect. Use of hard mask plays an important role in certain low-k integration schemes. The hard mask serves as a sacrificial layer atop of the low-k which avoid direct contact between low-k and photoresist to prevent resist poisoning, ensure low-k film withstands harsh resist rework conditions, and facilitate copper (Cu) chemical-mechanical polishing (CMP) for uniform processing control. Each interconnect level is separated by an inter-level dielectric (ILD). The individual interconnects within a single interconnect level are also separated by a dielectric material that may or may not be the same as the ILD. Vias or contacts are formed in the ILD and filled with conductive material to connect the interconnect levels in a specified pattern to achieve a desired functionality.
Various low-K materials have been used in low-K backend processing with mixed results. Integration of low-K material into existing fabrication processes is particularly challenging in the case of backend processing that includes the use of CMP. CMP is a technique by which each interconnect level is formed in many existing processes. In a CMP process, as implied by its name, a film or layer is physically polished with a rotating polishing pad in the presence of a “slurry” that contains mechanical abrasion components and/or chemical components to produce a smooth upper surface and to remove excess conductive material and thereby isolate the individual interconnects from one another.
One of the key patterning issues related to hard mask integration schemes is its overhang (or low-k undercut) after pattern transfer. The hard mask overhang is defined as the protruding part of hard mask at the trench top opening above the low-k dielectric. Formation of hard mask overhang is primarily related to post-trench-etch resist ash. During that step, the low-k surface at trench sidewall is modified, and an oxide-like layer is formed. Compared to hard mask or low-k film, this oxide-like layer is less resistant to the following wet etch cleaning step (usually a mild aqueous solution containing weak acidic buffer solutions). After wet etch cleaning, an overhang in the trench profile is formed by the removal of the oxide-like layer. A slower hard mask etch rate as compared to low-k film, also accounts for hard mask overhang. The overhang profile may degrade coverage of the copper liner process, and may leave copper voids under the overhang area. Exposed voids after copper CMP, form localized slit defects, may cause both yield loss and reliability degradation.
Thus, a need still remains for an integrated circuit hard mask processing system that integrates a low-K dielectric with a hard mask process that doesn't produce the slit defects, which may adversely impact yield and reliability. In view of the demand for smaller integrated circuit geometries and the increasing operational frequencies of the end devices, it is increasingly critical that answers be found to these problems. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.